| 1 | THE MICROPROCESSOR AND ITS ARCHITECTURE
• Internal Microprocessor Architecture
• The Programming Model
• Multipurpose Registers
• Real Mode Memory Addressing
• Segments and Offsets; Default Segment and Offset Registers
• Segment and Offset Addressing Scheme Allows Relocation
• Protected Mode Memory Addressing
• Selectors and Descriptors
• Program-Invisible Registers
• Memory Paging; Paging Registers;
The Page Directory and Page Table
• Flat Mode Memory |
| 2 | 8086/8088 HARDWARE SPECIFICATIONS
Pin-Outs and the Pin Functions
• The Pin-Out;
• Power Supply Requirements;
• DC Characteristics;
Clock Generator (8284A)
• The 8284A Clock Generator;
• Operation of the 8284A
Bus Buffering and Latching
• Demultiplexing the Buses;
• The Buffered System
Bus Timing
Basic Bus Operation;
• Timing in General;
• Read Timing;
• Write Timing
Ready and the Wait State
• The READY Input;
• RDY and the 8284A
Minimum Mode versus Maximum Mode
• Minimum Mode Operation;
• Maximum Mode Operation;
The 8288 Bus Controller |
| 3 | DATA MOVEMENT INSTRUCTIONS
ARITHMETIC AND LOGIC INSTRUCTIONS
PROGRAM CONTROL INSTRUCTIONS |
| 4 | ADDRESSING MODES
Data-Addressing Modes
• Register Addressing;
• Immediate Addressing;
• Direct Data Addressing;
• Register Indirect Addressing;
• Base-Plus-Index Addressing;
• Register Relative Addressing;
• Base Relative-Plus-Index Addressing;
• Scaled-Index Addressing;
• Relative Addressing;
• Data Structures
Program Memory-Addressing Modes
• Direct Program Memory Addressing;
• Relative Program Memory Addressing;
• Indirect Program Memory Addressing
Stack Memory-Addressing Modes |
| 5 | MEMORY INTERFACE
Memory Devices
• Memory Pin Connections;
• ROM Memory;
• Static RAM (SRAM) Devices;
• Dynamic RAM (DRAM) Memory
Address Decoding
• Simple NAND Gate Decoder;
• The 3-to-8 Line Decoder (74LS138);
• The Dual 2-to-4 Line Decoder (74LS139);
• PLD Programmable Decoders
8088 and 80188 (8-Bit) Memory Interface
• Basic 8088/80188 Memory Interface;
• Interfacing Flash Memory;
• Error Correction
8086, 80186, 80286, and 80386SX (16-Bit) Memory Interface
• 16-Bit Bus Control
80386DX and 80486 (32-Bit) Memory Interface
• Memory Banks;
• 32-Bit Memory Interface
Pentium through Core2 (64-Bit) Memory Interface
• 64-Bit Memory Interface
Dynamic RAM
DRAM Controllers |
| 6 | BASIC I/O INTERFACE
Introduction to I/O Interface
• The I/O Instructions;
• Isolated and Memory-Mapped I/O;
• Personal Computer I/O Map;
• Basic Input and Output Interfaces;
• Handshaking;
• Interfacing Circuitry
I/O Port Address Decoding
• Decoding 8-Bit I/O Port Addresses;
• Decoding 16-Bit I/O Port Addresses;
• 8- and 16-Bit-Wide I/O Ports;
• 32-Bit-Wide I/O Ports
The Programmable Peripheral Interface
• Basic Description of the 82C55;
• Programming the 82C55;
• Mode 0 Operation;
• An LCD Display, Interfaced to the 82C55;
• Mode 1 Strobed Input;
• Signal Definitions for Mode 1 Strobed Input;
• Mode 1 Strobed Output;
• Signal Definitions for Mode 1 Strobed Output;
• Mode 2 Bidirectional Operation;
• Signal Definitions for Bidirectional Mode 2;
• 82C55 Mode Summary;
• The Serial EEPROM Interface |
| 7 | BASIC I/O INTERFACE
8254 Programmable Interval Timer
• 8254 Functional Description;
• Programming the 8254;
• DC Motor Speed and Direction Control
16550 Programmable Communications Interface
• Asynchronous Serial Data;
• Functional Description;
• Programming the 16550
Analog-to-Digital (ADC) and Digital-to-Analog (DAC) Converters
• The DAC0830 Digital-to-Analog Converter;
• The ADC080X Analog-to-Digital Converter;
• Using the ADC0804 and the DAC0830 |
| 8 | Midterm exam |
| 9 | INTERRUPTS
Basic Interrupt Processing
• The Purpose of Interrupts;
• Interrupts;
• Interrupt Instructions: BOUND, INTO, INT, INT 3, and IRET;
• The Operation of a Real Mode Interrupt;
• Operation of a Protected Mode Interrupt;
• Interrupt Flag Bits;
• Storing an Interrupt Vector in the Vector Table
Hardware Interrupts
• INTR and INTA’;
• The 82C55 Keyboard Interrupt
Expanding the Interrupt Structure
• Using the 74ALS244 to Expand Interrupts;
• Daisy-Chained Interrupt
8259A Programmable Interrupt Controller
• General Description of the 8259A;
• Connecting a Single 8259A;
• Cascading Multiple 8259As;
• Programming the 8259A;
• 8259A Programming Example
Interrupt Examples
• Real-Time Clock;
• Interrupt-Processed Keyboard |
| 10 | DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
Basic DMA Operation
• Basic DMA Definitions
The 8237 DMA Controller
• Pin Definitions;
• Internal Registers;
• Software Commands;
• Programming the Address and Count Registers;
• The 8237 Connected to the 80X86 Microprocessor;
• Memory-to-Memory Transfer with the 8237;
• DMA-Processed Printer Interface
Shared-Bus Operation
• Types of Buses Defined;
• The Bus Arbiter;
• Pin Definitions
Disk Memory Systems
• Floppy Disk Memory;
• Pen Drives;
• Hard Disk Memory;
• Optical Disk Memory
Video Displays
• Video Signals;
• The TTL RGB Monitor;
• The Analog RGB Monitor |
| 11 | THE 80186, 80188, AND 80286 MICROPROCESSORS
80186/80188 Architecture
• Versions of the 80186/80188;
• 80186 Basic Block Diagram;
• 80186/80188 Basic Features;
• Pin-Out;
• DC Operating Characteristics;
• 80186/80188 Timing
Programming the 80186/80188 Enhancements
• Peripheral Control Block;
• Interrupts in the 80186/80188;
• Interrupt Controller;
• Timers;
• DMA Controller;
• Chip Selection Unit
80C188EB Example Interface
Introduction to the 80286
• Hardware Features;
• Additional Instructions;
• The Virtual Memory Machine |
| 12 | THE 80386 AND 80486 MICROPROCESSORS
Introduction to the 80386 Microprocessor
• The Memory System;
• The Input/Output System;
• Memory and I/O Control Signals;
• Timing;
• Wait States
Special 80386 Registers
• Control Registers;
• Debug and Test Registers
80386 Memory Management
• Descriptors and Selectors;
• Descriptor Tables;
• The Task State Segment (TSS)
Moving to Protected Mode
Virtual 8086 Mode
The Memory Paging Mechanism
• The Page Directory
• The Page Table
Introduction to the 80486 Microprocessor
• Pin-Out of the 80486DX and 80486SX Microprocessors;
• Basic 80486 Architecture;
• 80486 Memory System |
| 13 | THE PENTIUM AND PENTIUM PRO MICROPROCESSORS
Introduction to the Pentium Microprocessor
• The Memory System;
• Input/Output System;
• System Timing;
• Branch Prediction Logic;
• Cache Structure;
• Superscalar Architecture
Special Pentium Registers
• Control Registers;
• EFLAG Register;
• Built-In Self-Test (BIST)
Pentium Memory Management
• Paging Unit;
• Memory-Management Mode
• New Pentium Instructions
Introduction to the Pentium Pro Microprocessor
• Internal Structure of the Pentium Pro;
• Pin Connections;
• The Memory System;
• Input/Output System;
• System Timing
Special Pentium Pro Features
• Control Register
THE PENTIUM II, PENTIUM III, PENTIUM 4, AND CORE2 MICROPROCESSORS
Introduction to the Pentium II Microprocessor
• The Memory System;
• Input/Output System;
• System Timing
Pentium II Software Changes
• CPUID Instruction;
• SYSENTER and SYSEXIT Instructions;
• FXSAVE and FXRSTOR Instructions
The Pentium III
• Chip Sets;
• Bus;
• Pin-Out
The Pentium 4 and Core2
• Memory Interface;
• Register Set;
• Hyper-Threading Technology;
• Multiple Core Technology;
• CPUID;
• Model-Specific Registers;
• Performance-Monitoring Registers;
• 64-Bit Extension Technology |
| 14 | Review |
